1. Field of the Invention
The present invention relates to a clearance inspection apparatus and method for inspecting the clearance of wiring lines passing between vias on a substrate.
2. Description of the Related Art
In a semiconductor package such as a PBGA or EBGA package, a wiring pattern is designed so as to connect the pads (for example, bonding pads or flip chip pads), to be electrically connected to electrode terminals on a semiconductor chip, to the vias (lands) provided along the periphery thereof, or to connect between the vias.
As one example of a wiring pattern design method, there is disclosed in Japanese Unexamined Patent Publication No. 2002-083006 a method in which only wiring routes are determined in advance in a rough wiring step, and then, in a wiring forming step, the wiring lines are laid automatically and uniformly by considering clearances (lines and spaces) while checking them against the actual design rules.
Further, in Japanese Unexamined Patent Publication No. 10-214898, there is disclosed an automatic wiring method that employs an any-angle wiring technique to make effective use of wiring areas, while allowing wiring line spacing and wiring line width to be increased where space permits.
The result of automatic wiring differs depending on setting conditions. To address this, one possible design method is to determine which condition yields what wiring result, by changing the setting conditions for the nets between pads and vias or between vias in various ways, and to select the optimum setting conditions. Another possible design method is to change the positions of vias based on the result of the automatic wiring. In either case, the wiring lines passing between various kinds of obstacles, in particular, vias, must be inspected for wiring line spacing, i.e., the clearance (line and space). Usually, in a wiring line clearance inspection process, the clearance is inspected for every possible combination of vias.
FIG. 13 is a diagram showing one example of the inspection pattern illustrating the directions along which the wiring lines are to be inspected for clearance. In the figure, reference characters V1 to V10 are the identification numbers of the vias, and reference characters N1 to N13 are the identification numbers of the wiring lines. In the specification of the present invention, the direction along which a wiring line is inspected for clearance will be referred to as the “clearance inspection direction”, and the line showing the clearance inspection direction as the “inspection line”.
When the wiring lines N1 to N13 are routed in accordance with design data on a substrate where the vias V1 to V10 are formed, the wiring lines N1 to N13 must be inspected for clearance along the clearance inspection directions indicated by the inspection lines shown by dashed lines in the figure. Here, as the clearance inspection is performed for every possible combination of vias, there are as many clearance inspection directions as there are possible combinations of the vias. For example, as shown in FIG. 13, there are very many inspection lines (each shown by a dashed line in the figure).
FIGS. 14a and 14b are diagrams showing another example of the inspection pattern illustrating the directions along which the wiring lines are to be inspected for clearance. In the figure, reference characters V1 to V11 are the identification numbers of the vias, reference characters N1 to N8 are the identification numbers of the wiring lines, and reference characters A1 and A2 are the identification numbers of auxiliary lines (indicated by semi-dashed lines in the figure).
When the wiring lines N1 to N8 are routed passing between the vias V1 to V11 as shown in FIG. 14a, the wiring lines N1 to N8 are inspected for clearance along the clearance inspection directions indicated by the inspection lines shown by dashed lines in the figure.
As earlier described, the clearance inspection directions are determined by the possible combinations of the vias V1 to V11. However, between the vias V8 and V11, for example, there is no wiring line passing between them and, in actuality, there is no need to inspect the wiring line clearance between these vias V8 and V11. Further, in the space between the vias V10 and V3 and between the vias V10 and V4; while the wiring lines N4 to N8 are routed passing through the space, there is no wiring line passing between the vias V3 and V4. Accordingly, once the clearance inspection is performed between the vias V10 and V4, the clearance inspection need not necessarily be performed between the vias V10 and V3.
While, in automatic wiring, it is desirable to be able to obtain the result of the clearance inspection instantly, if the clearance inspection is to be performed for every possible combination of vias, the amount of computation will become enormous, leading to the problem that it takes considerable time to complete the inspection. Here, if the clearance inspection is performed only for those combinations of vias between which the wiring lines pass, unnecessary clearance inspection can be eliminated, and it should become possible to reduce the amount of the computation to be performed by a computer. FIG. 14b shows one example of the inspection pattern after the number of clearance inspection directions has been reduced.
Accordingly, in view of the above problem, it is an object of the present invention to provide a clearance inspection method and apparatus that can efficiently inspect the clearance of wiring lines passing between vias on a substrate.